About

I am a member of the CSDL Lab, supervised by Prof. Seokhyeong Kang, in the Department of Electrical Engineering at Pohang University of Science and Technology (POSTECH). Since July 2026, I am currently an on-site Visiting Graduate Scholar with the ABKGroup (VLSI CAD Laboratory) at the University of California San Diego, hosted by Prof. Andrew B. Kahng. My research focuses on differentiable optimization frameworks for VLSI CAD objectives and AI-driven approaches to electronic design automation. I received my B.S. in Electrical Engineering and M.S. from the Graduate School of AI at POSTECH. During my M.S., I was supervised by Prof. Jaesik Park in the Computer Vision Lab.

Research Interests

AI for EDADifferentiable OptimizationPhysical Design AutomationTiming OptimizationMachine Learning

Education

University of California San Diego (UC San Diego)

Jul 2026 – Present

Visiting Graduate Scholar · ABKGroup (VLSI CAD Laboratory)

On-site · La Jolla, CA · Supervisor: Prof. Andrew B. Kahng

Pohang University of Science and Technology (POSTECH)

Current

Ph.D. Candidate in Electrical Engineering

Pohang, Korea · Supervisor: Prof. Seokhyeong Kang

Pohang University of Science and Technology (POSTECH)

Sep 2020 – Feb 2023

M.S. in Graduate School of AI

Pohang, Korea · Thesis: Instance-Aware Image Completion · Supervisor: Prof. Jaesik Park

Pohang University of Science and Technology (POSTECH)

Mar 2016 – Aug 2020

B.S. in Electrical Engineering

Pohang, Korea

Publications

1

Timing- and Power-Aware Differentiable Repair of Minimum Implant Area Violations

Jinoh Cho, Minhyuk Kweon, Jinmo Ahn, Jeyeong Park, and Seokhyeong Kang

ACM/IEEE ISLPED, Evanston, IL, USA, 2026

2

Differentiable Fill Insertion with Explicit Delay Optimization

Jinoh Cho, Jinmo Ahn, Jakang Lee, Jaeseung Lee, Seonghyeon Park, and Seokhyeong Kang

ACM/IEEE DAC, Long Beach, CA, USA, 2026

3

CTRL-B: Back-End-Of-Line Configuration Optimization using Cross-Domain Transferable Reinforcement Learning

Jaeseung Lee, Sung-Yun Lee, Jinoh Cho, Daijoon Hyun, and Seokhyeong Kang

IEEE TCAD, 2026

4

A Heterogeneous Graph-based Gate Sizer Integrating Graph Attention Network and Transformer

Jinmo Ahn, Jinoh Cho, Jaemin Seo, Jaeseung Lee, Jakang Lee, and Seokhyeong Kang

ASP-DAC, Hong Kong, 2026

5

Improving LLM-based Verilog Code Generation with Data Augmentation and RL

Kyungjun Min, Seonghyeon Park, Hyeonwoo Park, Jinoh Cho, and Seokhyeong Kang

DATE, Lyon, France, 2025

6

Leveraging Machine Learning Techniques for Traditional EDA Workflow Enhancement

Jinoh Cho, Jaekyung Im, Jaeseung Lee, Kyungjun Min, Seonghyeon Park, Jaemin Seo, Jongho Yoon, and Seokhyeong Kang

ASP-DAC, Tokyo, Japan, 2025

7

RL-Fill: Timing-Aware Fill Insertion using Reinforcement Learning

Jinoh Cho, Seonghyeon Park, Jakang Lee, Sung-Yun Lee, Jinmo Ahn, and Seokhyeong Kang

ICCAD, Newark, USA, 2024

8

Timing-Aware 3D IC Partitioning and Placement by Optimizing the Critical Path

Donggyu Kim, Minjae Kim, Junseok Hur, Jakang Lee, Jinoh Cho, and Seokhyeong Kang

MLCAD, Snowbird, UT, USA, 2024

9

Instance-Aware Image Completion

Jinoh Cho, Minguk Kang, Vibhav Vineet, and Jaesik Park

CVPR Workshops, Vancouver, Canada, 2023

Experience

Samsung Electronics

Jan 2020 – Feb 2020

Research Intern · CE/IM Visual Display, SoC H/W Team

LG Display

Jun 2018 – Jul 2018

Research Intern · OLED Encapsulation Team

Awards & Honors

2026

Encouragement Award, 32nd Samsung HumanTech Paper Award

Jinoh Cho, Jinmo Ahn, and Seokhyeong Kang · Top 3.8% among 3,172 submissions

2025

3rd Prize, 4th POSTECH-EE Research Achievement Sharing and Award

Research Achievement Award

2021

Excellence Award, Artificial Intelligence Diabetes Datathon

Team leader · AI model development challenge for diabetes prediction

Skills & Proficiency

Programming: Python, C, C++, Verilog
Research: Differentiable optimization, reinforcement learning, graph neural networks, computer vision
Languages: Korean (native), English (professional)
Interests: Soccer and tennis