Career Profile

At present, I am affiliated with the CSDL lab under Prof. Seokhyeong Kang in the Department of Electrical Engineering at Pohang University of Science and Technology (POSTECH), South Korea. My area of research revolves around the adoption of AI for VLSI CAD (Computer-Aided Design). Previously, I received B.S. and M.S. degree in Electrical Engineering and Graduate School of AI (GSAI) both from POSTECH, respectively. While pursuing master degree, I was advised by Prof. Jaesik Park in the Computer Vision Lab at POSTECH.

Education

M.S. in Graduate School of AI

2020.09 - 2023.02
Pohang University of Science and Technology (POSTECH)
  • Under the supervision of Prof.Jaesik Park in Computer Vision Lab.
  • Thesis : Instance-Aware Image Completion

B.S. in Electrical Engineering

2016.03 - 2020.08
Pohang University of Science and Technology (POSTECH)

Experiences

Internship

2020.01 - 2020.02
Samsung Electronics CE/IM Visual Display (VD), SoC H/W Team

Internship

2018.06 - 2018.07
LG Display, OLED Encap. Team

Publications

  • Timing-Aware Fill Insertion using Reinforcement Learning
  • Jinoh Cho, Seonghyeon Park, Jakang Lee, Sung-Yun Lee, Jinmo Ahn, and Seokhyeong Kang
    ACM/IEEE International Conference on Computer-Aided Design (ICCAD), Newark, USA, 2024
  • Timing-Aware 3D IC Partitioning and Placement by Optimizing the Critical Path
  • Donggyu Kim, Minjae Kim, Junseok Hur, Jakang Lee, Jinoh Cho, and Seokhyeong Kang
    ACM/IEEE International Symposium on Machine Learning for CAD (MLCAD), Snowbird, USA, 2024
  • Instance-Aware Image Completion
  • Jinoh Cho, Minguk Kang, Vibhav Vineet, Jaesik Park
    IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshop (CVPRW), Vancouver, Canada, 2023

    Awards

  • Exellence Award in Artificial Intelligence Diabetes Datathon 2021 (A.I.D.D 2021)
  • Jinoh Cho, Hyunjun Lee, Kang Gun
    Participate as a Team Leader, AI Model Development Challenge for Diabetes Prediction on NSML(Naver Smart Machine Learning) platform.

    Skills & Proficiency

    Python

    C & C++

    Verilog